A semiconductor device which includes a memory cell region in which a memory cell, for example, a non-volatile memory or the like, is formed on a semiconductor substrate, and a peripheral circuit region in which a peripheral circuit constituted by, for example, a metal insulator semiconductor field effect transistor (MISFET) or the like, is formed on the semiconductor substrate, has been widely used.
For example, a memory cell constituted by a split gate cell made of a metal-oxide-nitride-oxide-semiconductor (MONOS) film is sometimes formed as the non-volatile memory. This memory cell is formed using two MISFET's including a control transistor which has a control gate electrode, and a memory transistor which has a memory gate electrode. In addition, a gate insulating film of the memory transistor is made up of a laminate film which includes, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film and is referred to as an oxide nitride oxide (ONO) film.
Further, a voltage higher than a power supply voltage which is supplied from the outside of the semiconductor device is required for an electrical write or erase operation with respect to the non-volatile memory, and thus, a booster circuit which includes a capacitive element is formed in a peripheral circuit region of the semiconductor device. In addition, a bypass capacitor (capacitive element) which is connected between a power supply wire (Vcc) and a ground wire (Gnd) of the semiconductor device in order for stabilization of power supply is also built in the semiconductor device. A polysilicon insulator polysilicon (PIP) capacitive element which has a favorable consistency with a manufacturing process of the memory cell is used as these capacitive elements.
Japanese Patent Application Laid-Open Publication No. 2009-99640 (Patent Document 1) discloses a non-volatile memory cell which includes a control gate electrode (corresponding to the above-described control gate electrode) 15, a memory gate electrode 26, and a laminate film (corresponding to the above-described ONO film) provided between the control gate electrode 15 and a semiconductor substrate 10, and the memory gate electrode 26. In addition, a capacitive element constituted by a lower electrode 16, a capacitor insulating film 27, and an upper electrode 23 is also disclosed. Further, a method is disclosed in which the control gate electrode 15 of the memory cell and the lower electrode 16 of the capacitive element are formed of a polysilicon film 14, the memory gate electrode 26 of the memory cell and the upper electrode 23 of the capacitive element are formed of a polysilicon film 20, and the capacitor insulating film 27 of the capacitive element is formed of the laminate film of the memory cell.
Japanese Patent Application Laid-Open Publication No. 2014-229844 (Patent Document 2) discloses a non-volatile memory cell which includes a control gate electrode (corresponding to the above-described control gate electrode) 15, a memory gate electrode 26, and an insulating film 27a. In addition, a capacitive element, which includes an electrode 16, a capacitive insulating film 27, and an electrode 23, is also disclosed. Further, a method is disclosed in which the control gate electrode 15 of the memory cell and the electrode 16 of the capacitive element are formed of a conductor film CF1, the memory gate electrode 26 of the memory cell and the electrode 23 of the capacitive element are formed of a conductor film CF2, and the capacitive insulating film 27 of the capacitive element is formed of the insulating film 27a of the memory cell. In addition, a structure is disclosed in which the electrode 23 is disposed on a sidewall of the electrode 16 via the capacitive insulating film 27.